1. Field of the Invention
The present invention relates to a computer system constituted of a plurality of CPU units interconnected by a serial connect bus, and a method for interconnecting a plurality of CPU units by means of a serial connect bus, and more particularly, a computer system in which units are interconnected by a serial connect switch having an upstream port being set for system initialization, and a method for interconnecting a plurality of CPU units by means of a serial connect bus.
2. Description of the Related Art
In recent years, because of an expanded use of electronic data, data amount to be processed by computer systems is abruptly increasing. To cope with such demand, there is ongoing development on interconnect (internal connection) technology for interconnecting inside the computer system, so as to obtain high-speed and large-capacity data transfer.
Such interconnect technology is employed in both an LSI and a printed circuit board, and is widely utilized as an interconnect means inside the computer system. A typical example having been widely used is a PCI (peripheral component interconnect) bus for parallel data transfer.
FIG. 9 shows a computer system configuration using the conventional PCI bus. A CPU (central processing unit) 100 is connected to a memory (main memory) 104 and an input/output controller (I/O controller) 104 via a memory controller 102. The I/O controller 104 has a plurality of PCI buses 108-1, 108-2. PCI buses 108-1, 108-2 have PCI slots 106-1-106-4.
In these PCI slots 106-1-106-4, cards having PCI devices (mainly peripheral devices) mounted thereon are inserted. The operating frequency of this PCI bus ranges from 33 MHz to 133 MHz, with two types of bus widths, 32 bits and 64 bits. Total bus bandwidths in the both directions per slot become 1 gigabyte per second (GB/s) maximum.
In contrast to this parallel PCI bus, it is considered that a serial-type interconnect will become a mainstream in the near future, because of a low mounting cost in addition to high-speed and large-capacity. Particularly, a PCI Express bus, a serial interconnect bus, has been developed by the PCI-SIG (PCI Special Interest Group) as the successor to the PCI bus. The PCI Express bus is expected to be used in a variety of computer systems, ranging from desktop computers to large-scale servers and storage systems.
FIG. 10 shows a configuration diagram of a computer system using the conventional PCI Express bus. The CPU 100 is connected to the memory 104 via the memory controller 102. This memory controller 102 has a plurality of PCI Express buses 110-1-110-4. A card having a PCI Express bus device mounted thereon can be installed on each PCI Express bus slot 106-1-106-4.
These PCI Express buses 110-1-110-4 are serial transfer buses each having an upward path and a downward path, mutually separated from each other. Because of differential type, the number of signal lines is four in total. To perform packet transfer serially, the bandwidth per slot is 1 GB/s in one direction, which is twice as large as the bandwidth provided in the PCI bus.
As such, because the number of signal lines in the PCI Express bus is smaller than in the PCI bus, reduction of chip sets, wires on a substrate and a connector size can be attained, each contributing to the cost reduction. At the same time, the bandwidth provision more than twice as large as the PCI bandwidth can satisfy requirements of high speed and high performance.
This PCI Express bus logically inherits the PCI bus architecture (the connection of peripheral devices). According to the standard of the PCI Express bus, similarly to a USB hub, one port in a switch for switching a connection path in the memory controller acts a special role, such as for the initialization of the overall system, which is termed ‘upstream port’. (For example, refer to the Japanese Unexamined Patent Publication No. 2001-229119).
In normal cases, in the configuration shown in FIG. 10, one CPU 100 is connected to the upstream port so as to use the PCI Express bus (namely, a serial interconnect bus for peripheral devices), because one CPU 100 connects to peripheral devices.
As described above, the serial interconnect such as the PCI Express bus is expected to be used in a various field as high-performance and low-cost interconnect. However, originally, the PCI Express bus has been aimed at connecting peripheral devices to a CPU. When the PCI Express bus is aimed at use for interconnecting a plurality of CPUs, there is a problem to be solved when it is intended to apply the PCI Express bus without modification.
Namely, when connecting a plurality of CPU nodes using a PCI Express switch having a plurality of ports, a privileged role is assigned to a particular CPU node which is connected to the upstream port of the switch. Without this CPU node, the PCI Express switch cannot perform an initialization operation (link establishment).
Meanwhile, in a server or a storage system constituted of a plurality of CPU nodes, in order to increase flexibility, CPU nodes are treated as units of which number can be either increased or decreased depending on a product configuration. Therefore, if this particular CPU does not exist in the system, the switch cannot be operated, and as a result the system cannot be operated. So, it becomes difficult to increase or decrease CPU nodes freely. Such a situation has to be avoided if possible.
Further, when a malfunction occurs in the CPU node connected to the upstream port, the PCI Express switch cannot be operated, which also causes difficulty in the system operation.